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Fix build on aarch64

pull/30/head
Merry 2022-02-15 17:49:32 +00:00
parent 2cf18d5aab
commit cb5bf64515
16 changed files with 41 additions and 28 deletions
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1
qemu/aarch64.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_aarch64
#define tb_reset_jump tb_reset_jump_aarch64
#define tb_set_jmp_target tb_set_jmp_target_aarch64
#define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64
#define tcg_accel_class_init tcg_accel_class_init_aarch64
#define tcg_accel_type tcg_accel_type_aarch64
#define tcg_add_param_i32 tcg_add_param_i32_aarch64

1
qemu/aarch64eb.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_aarch64eb
#define tb_reset_jump tb_reset_jump_aarch64eb
#define tb_set_jmp_target tb_set_jmp_target_aarch64eb
#define tb_target_set_jmp_target tb_target_set_jmp_target_aarch64eb
#define tcg_accel_class_init tcg_accel_class_init_aarch64eb
#define tcg_accel_type tcg_accel_type_aarch64eb
#define tcg_add_param_i32 tcg_add_param_i32_aarch64eb

1
qemu/arm.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_arm
#define tb_reset_jump tb_reset_jump_arm
#define tb_set_jmp_target tb_set_jmp_target_arm
#define tb_target_set_jmp_target tb_target_set_jmp_target_arm
#define tcg_accel_class_init tcg_accel_class_init_arm
#define tcg_accel_type tcg_accel_type_arm
#define tcg_add_param_i32 tcg_add_param_i32_arm

1
qemu/armeb.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_armeb
#define tb_reset_jump tb_reset_jump_armeb
#define tb_set_jmp_target tb_set_jmp_target_armeb
#define tb_target_set_jmp_target tb_target_set_jmp_target_armeb
#define tcg_accel_class_init tcg_accel_class_init_armeb
#define tcg_accel_type tcg_accel_type_armeb
#define tcg_add_param_i32 tcg_add_param_i32_armeb

2
qemu/configure vendored
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@ -1528,7 +1528,7 @@ elif test "$ARCH" = "ppc64" ; then
elif test "$ARCH" = "riscv32" || test "$ARCH" = "riscv64" ; then
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES"
else
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES"
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/$ARCH $QEMU_INCLUDES"
fi
QEMU_INCLUDES="-I\$(SRC_PATH)/tcg $QEMU_INCLUDES"

1
qemu/header_gen.py
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@ -2947,6 +2947,7 @@ symbols = (
'tb_phys_invalidate',
'tb_reset_jump',
'tb_set_jmp_target',
'tb_target_set_jmp_target',
'tcg_accel_class_init',
'tcg_accel_type',
'tcg_add_param_i32',

1
qemu/m68k.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_m68k
#define tb_reset_jump tb_reset_jump_m68k
#define tb_set_jmp_target tb_set_jmp_target_m68k
#define tb_target_set_jmp_target tb_target_set_jmp_target_m68k
#define tcg_accel_class_init tcg_accel_class_init_m68k
#define tcg_accel_type tcg_accel_type_m68k
#define tcg_add_param_i32 tcg_add_param_i32_m68k

1
qemu/mips.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_mips
#define tb_reset_jump tb_reset_jump_mips
#define tb_set_jmp_target tb_set_jmp_target_mips
#define tb_target_set_jmp_target tb_target_set_jmp_target_mips
#define tcg_accel_class_init tcg_accel_class_init_mips
#define tcg_accel_type tcg_accel_type_mips
#define tcg_add_param_i32 tcg_add_param_i32_mips

1
qemu/mips64.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_mips64
#define tb_reset_jump tb_reset_jump_mips64
#define tb_set_jmp_target tb_set_jmp_target_mips64
#define tb_target_set_jmp_target tb_target_set_jmp_target_mips64
#define tcg_accel_class_init tcg_accel_class_init_mips64
#define tcg_accel_type tcg_accel_type_mips64
#define tcg_add_param_i32 tcg_add_param_i32_mips64

1
qemu/mips64el.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_mips64el
#define tb_reset_jump tb_reset_jump_mips64el
#define tb_set_jmp_target tb_set_jmp_target_mips64el
#define tb_target_set_jmp_target tb_target_set_jmp_target_mips64el
#define tcg_accel_class_init tcg_accel_class_init_mips64el
#define tcg_accel_type tcg_accel_type_mips64el
#define tcg_add_param_i32 tcg_add_param_i32_mips64el

1
qemu/mipsel.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_mipsel
#define tb_reset_jump tb_reset_jump_mipsel
#define tb_set_jmp_target tb_set_jmp_target_mipsel
#define tb_target_set_jmp_target tb_target_set_jmp_target_mipsel
#define tcg_accel_class_init tcg_accel_class_init_mipsel
#define tcg_accel_type tcg_accel_type_mipsel
#define tcg_add_param_i32 tcg_add_param_i32_mipsel

1
qemu/sparc.h
View File

@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_sparc
#define tb_reset_jump tb_reset_jump_sparc
#define tb_set_jmp_target tb_set_jmp_target_sparc
#define tb_target_set_jmp_target tb_target_set_jmp_target_sparc
#define tcg_accel_class_init tcg_accel_class_init_sparc
#define tcg_accel_type tcg_accel_type_sparc
#define tcg_add_param_i32 tcg_add_param_i32_sparc

1
qemu/sparc64.h
View File

@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_sparc64
#define tb_reset_jump tb_reset_jump_sparc64
#define tb_set_jmp_target tb_set_jmp_target_sparc64
#define tb_target_set_jmp_target tb_target_set_jmp_target_sparc64
#define tcg_accel_class_init tcg_accel_class_init_sparc64
#define tcg_accel_type tcg_accel_type_sparc64
#define tcg_add_param_i32 tcg_add_param_i32_sparc64

54
qemu/tcg/aarch64/tcg-target.inc.c
View File

@ -1871,7 +1871,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
{
/* 99% of the time, we can signal the use of extension registers
by looking to see if the opcode handles 64-bit data. */
TCGType ext = (tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
TCGType ext = (s->tcg_op_defs[opc].flags & TCG_OPF_64BIT) != 0;
/* Hoist the loads of the most common arguments. */
TCGArg a0 = args[0];
@ -1922,7 +1922,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_br:
tcg_out_goto_label(s, arg_label(a0));
tcg_out_goto_label(s, arg_label(s, a0));
break;
case INDEX_op_ld8u_i32:
@ -2154,7 +2154,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
a1 = (int32_t)a1;
/* FALLTHRU */
case INDEX_op_brcond_i64:
tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(args[3]));
tcg_out_brcond(s, ext, a2, a0, a1, const_args[1], arg_label(s, args[3]));
break;
case INDEX_op_setcond_i32:
@ -2835,31 +2835,31 @@ static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
static void tcg_target_init(TCGContext *s)
{
tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
s->tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffffu;
s->tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffffu;
s->tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
s->tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull;
tcg_target_call_clobber_regs = -1ull;
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X19);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X20);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X21);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X22);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X23);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X24);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X25);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X26);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X27);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X28);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_X29);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V8);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V9);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V10);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V11);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V12);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V13);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V14);
tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V15);
s->tcg_target_call_clobber_regs = -1ull;
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X19);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X20);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X21);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X22);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X23);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X24);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X25);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X26);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X27);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X28);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_X29);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V8);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V9);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V10);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V11);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V12);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V13);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V14);
tcg_regset_reset_reg(s->tcg_target_call_clobber_regs, TCG_REG_V15);
s->reserved_regs = 0;
tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);

0
qemu/tcg/aarch64/tcg-target-opc.h → qemu/tcg/aarch64/tcg-target.opc.h
View File

1
qemu/x86_64.h
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@ -2941,6 +2941,7 @@
#define tb_phys_invalidate tb_phys_invalidate_x86_64
#define tb_reset_jump tb_reset_jump_x86_64
#define tb_set_jmp_target tb_set_jmp_target_x86_64
#define tb_target_set_jmp_target tb_target_set_jmp_target_x86_64
#define tcg_accel_class_init tcg_accel_class_init_x86_64
#define tcg_accel_type tcg_accel_type_x86_64
#define tcg_add_param_i32 tcg_add_param_i32_x86_64